The present invention relates to graphics processors which support scrolling windows.
Graphics processor boards control the display on a monitor using special video RAMs. These chips are similar to conventional dynamic RAMs, but they have an internal shift register that can be loaded from an entire row of bits in the RAM array in a single cycle. The shift register data can then be serially clocked out on a separate pin, while the memory portion of the chip continues to perform random read and write cycles. The selection of a row to be transferred to the video RAM shift register is done using a RAS signal from a graphics processor. One graphics processor specially designed for working with video RAMs is the Texas Instruments' 34010. The 34010 outputs a signal called TRQE-L which indicates the start of shift register transfer cycle. Data is transferred out of the shift register serially starting from a column address indicated during a CAS signal from the processor. To accomplish scrolling, the column address signal is simply changed to indicate the appropriate starting position for the amount of scrolling desired.
The video memory is organized as a scrolling plane and a static plane. The static plane is normally visible as the "foreground". Windows can be written in the static plane to make the scrolling plane visible. A typical configuration for accomplishing this is shown in FIG. 1.
FIG. 1 shows a microprocessor 10 with system RAM 12. The processor provides control signals to video RAM 14. Processor 10 will provide the TRQE signal to indicate a shift register transfer cycle, followed by a row address and RAS signal specifying which row to transfer. Then the column address and CAS signal indicate from where in the shift register data is to start. The outputs of the video RAM 14 are provided to a color palette look-up table 18. Windows can be generated in software, with the combined window and background provided by the processor. Overlays are generated by writing zeros into the overlay location in the VRAM 14. Look-up table 18 will then compare the pixel bits and substitute the overlay data when there is a zero in the VRAM data.
One such look-up table is the Brooktree BT478, which is shown in block diagram form in FIG. 2. The look-up table contains a color palette RAM 20 which stores color values for data coming in. The data comes in through a latch 22 which provides both the normal video data on the upper bus (PO-P7) and the overlay data on the lower bus (OL0-OL3). The video data is passed through a mask register 24 to set any unused input bits to zero. Outputs are provided in analog form through digital-to-analog converters. The color palette RAM will compare the normal video and overlay data and substitute the overlay data output when zeros are detected for normal video data pixels.